// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  glb_cfg_axi_reg_offset.h
// Project line  :  K3
// Department    :  K3
// Author        :  Huawei
// Version       :  V100
// Date          :  2015/4/10
// Description   :  HiVcodecV100 VDEC
// Others        :  Generated automatically by nManager V4.2 
// History       :  Huawei 2018/04/10 10:02:43 Create file
// ******************************************************************************

#ifndef __GLB_CFG_AXI_REG_OFFSET_H__
#define __GLB_CFG_AXI_REG_OFFSET_H__

/* GLB_CFG_AXI Base address of Module's Register */
#define SOC_GLB_CFG_AXI_BASE                       (0xe800)

/******************************************************************************/
/*                      SOC GLB_CFG_AXI Registers' Definitions                            */
/******************************************************************************/

#define SOC_GLB_CFG_AXI_EMAR_OUTSANDING_REG       (SOC_GLB_CFG_AXI_BASE + 0x0)  
#define SOC_GLB_CFG_AXI_ALL_R_MID_RRMAX_REG       (SOC_GLB_CFG_AXI_BASE + 0x4)  
#define SOC_GLB_CFG_AXI_R_BG_ADJUST_REG           (SOC_GLB_CFG_AXI_BASE + 0x8)  
#define SOC_GLB_CFG_AXI_VDH_FORCE_REQ_ACK_AXI_REG (SOC_GLB_CFG_AXI_BASE + 0xC)  
#define SOC_GLB_CFG_AXI_ALL_R_MID_INFO_REG        (SOC_GLB_CFG_AXI_BASE + 0x40) 
#define SOC_GLB_CFG_AXI_ALL_W_MID_INFO_REG        (SOC_GLB_CFG_AXI_BASE + 0x44) 
#define SOC_GLB_CFG_AXI_AXI_SOFTRST_STATE0_REG    (SOC_GLB_CFG_AXI_BASE + 0x48) 
#define SOC_GLB_CFG_AXI_AXI_SOFTRST_STATE1_REG    (SOC_GLB_CFG_AXI_BASE + 0x4C) 

#endif // __GLB_CFG_AXI_REG_OFFSET_H__
